The present invention generally relates to complementary metal-oxide-semiconductor (CMOS) fabrication methods and related structures. More specifically, the present invention relates to methods and device architectures for fabricating diodes and transistors that can be integrated with nanosheet CMOS structures, thus allowing the formation of on-chip diodes with increased junction areas at the same time as forming nanosheet transistors.
In contemporary semiconductor device fabrication processes, a large number of devices, including field effect transistors (FETs), are fabricated on a single wafer. In addition to these devices, there is a need for other structures, such as diodes, that are formed from PN junctions. Being fabricated from similar materials, it is advantageous to be able to form both FETs and diodes onto a substrate by applying the same processes onto the same structure and on the same layer, including nanosheet layers. In nanosheet-based transistors (or nanowire-based transistors), in contrast to conventional FETs, the gate stack wraps around the full perimeter of each nanosheet (or nanowire), enabling fuller depletion in the channel region, and reducing short-channel effects due to steeper sub-threshold swing (SS) and smaller drain-induced barrier lowering (DIBL). Diodes fabricated from nanosheet structures also increase the PN junction area per footprint.